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EN27C020 4800 great america parkway ste 202 tel: 408-235-8680 santa clara, ca. 95054 fax: 408-235-8685 preliminary 1 features fast read access time : - 45, -55, -70, and -90ns single 5v power supply programming voltage +12.75v quikrite tm programming algorithm typical programming time 20 m s low power cmos operation 1 m a standby (typical) 30ma operation (max.) cmos- and ttl-compatible i/o high-reliability cmos technology latch-up immunity to 100ma from -1v to v cc + 1v two-line control ( oe & ce ) standard product identification code jedec standard pinout 32-pin pdip 32-pin plcc 32-pin tsop (type 1) commercial and industrial temperature ranges general description the EN27C020 is a low-power 2-megabit, 5v-only one-time-programmable (otp) read-only memory (eprom). organized into 256k words with 8 bits per word, it features quikrite tm single- address location programming, typically at 20 m s per byte. any byte can be accessed in less than 45ns, eliminating the need for wait states in high-performance microprocessor systems. the EN27C020 has separate output enable ( oe ) and chip enable ( ce ) controls which eliminate bus contention issues. figure 1. pdip pin name function a0-a17 addresses dq0-dq7 outputs ce chip enable oe output enable pgm program strobe a17 EN27C020 2megabit eprom (256k x 8)
EN27C020 4800 great america parkway ste 202 tel: 408-235-8680 santa clara, ca. 95054 fax: 408-235-8685 preliminary 2 figure 2. tsop figure 3. plcc tsop EN27C020 a17 plcc top view a12 a16 vcc a17 a15 vpp pg m
EN27C020 4800 great america parkway ste 202 tel: 408-235-8680 santa clara, ca. 95054 fax: 408-235-8685 preliminary 3 figure 4. block diagram functional description the quikrite tm programming of the EN27C020 when the EN27C020 is delivered, the chip has all 2m bits in the one, or high state. zeros are loaded into the EN27C020 through the procedure of programming. the programming mode is entered when 12.75 0.25v is applied to the v pp pin, oe is at v ih , and ce and pgm are at v il . for programming, the data to be programmed is applied with 8 bits in parallel to the data pins. the quikrite tm programming flowchart in figure 5 shows eons interactive programming algorithm. the interactive algorithm reduces programming time by using 20 m s to 100 m s programming pulses and giving each address only as many pulses as is necessary in order to reliably program the data. after each pulse is applied to a given address, the data in that address is verified. if the data is not verified, additional pulses are given until it is verified or until the maximum number of pulses is reached. this process is repeated while sequencing through each address of the EN27C020. this part of the programming algorithm is done at v cc = 6.25v to assure that each eprom bit is programmed to a sufficiently high threshold voltage. this ensures that all bits have sufficient margin. after the final address is completed, the entire eprom memory is read at v cc = v pp = 5.25 0.25v to verify the entire memory. control logic input/ output buffers y-decoder x-decoder y-select 2m bit cell matrix vcc vpp vss a0 - a17 address inputs dq0 - dq7 8 1024 2048 ce pgm oe
EN27C020 4800 great america parkway ste 202 tel: 408-235-8680 santa clara, ca. 95054 fax: 408-235-8685 preliminary 4 program inhibit mode programming of multiple EN27C020 in parallel with different data is also easily accomplished by using the program inhibit mode. except for ce , all like inputs of the parallel EN27C020 may be common. a ttl low-level program pulse applied to an EN27C020 ce input with v pp = 12.75 0.25v pgm low, and oe high will program that EN27C020. a high -level ce input inhibits the other EN27C020 from being programmed. program verify mode verification should be performed on the programmed bits to determining that they were correctly programmed. the verification should be performed with oe and ce at v il , pgmat v ih , and v pp at it programming voltage. auto product identification the auto product identification mode allows the reading out of a binary code from an eprom that will identify its manufacturer and type. this mode is intended for use by programming equipment for the purpose of automatically matching the device to be programmed with its corresponding programming algorithm. this mode is functional in the 25 c 5 c ambient temperature range that is required when programming the EN27C020. to activate this mode, the programming equipment must force 12.0 v 0.5v on address line a9 of the EN27C020. two identifier bytes may then be sequenced from the device outputs by toggling address line a0 from v il to v ih , when a1 = v ih . all other address lines must be held at v il during auto product identification mode. byte 0 (a0 = v il ) represents the manufacturer code, and byte 1 (a0 = v ih ), the device code. for the EN27C020, these two identifiers bytes are given in the mode select table. all identifiers for manufacturer and device codes will possess odd parity, with the msb (dq7) defined as the parity bit. when a1 = v il , the EN27C020 will read out the binary code of 7f, continuation code, to signify the unavailability of manufacturer id codes.
EN27C020 4800 great america parkway ste 202 tel: 408-235-8680 santa clara, ca. 95054 fax: 408-235-8685 preliminary 5 read mode the EN27C020 has two control functions, both of which must be logically satisfied in order to obtain data at the outputs. chip enable ( ce ) is the power control and should be used for device selection. output enable ( oe ) is the output control and should be used to gate data to the output pins, independent of device selection. assuming that addresses are stable, address access time (t acc ) is equal to the delay from ce to output (t ce ) . data is available at the outputs (t oe ) after the falling edge of oe , assuming the ce has been low and addresses have been stable for at least t acc - t oe . standby mode the EN27C020 has cmos standby mode which reduces the maximum v cc current to 20 m a. it is placed in cmos standby when ce is at v cc 0.3 v. the EN27C020 also has a ttl- standby mode which reduces the maximum v cc current to 1.0 ma. it is placed in ttl- standby when ce is at v ih . when in standby mode, the outputs are in a high-impedance state, independent of the oe input. two-line output control function to accommodate multiple memory connections, a two-line control function is provided to allow for: 1. low memory power dissipation, 2. assurance that output bus contention will not occur. it is recommended that ce be decoded and used as the primary device-selection function, while oe be made a common connection to all devices in the array and connected to the read line from the system control bus. this assures that all deselected memory devices are in their low-power standby mode and that the output pins are only active when data is desired from a particular memory device. system considerations during the switch between active and standby conditions, transient current peaks are produced on the rising and falling edges of chip enable. the magnitude of these transient current peaks is dependent on the output capacitance loading of the device. at a minimum, a 0.1 m f ceramic capacitor (high frequency, low inherent inductance) should be used on each device between vcc and vss to minimize transient effects. in addition, to overcome the voltage drop caused by the inductive effects of the printed circuit board traces on eprom arrays, a 4.7 m f bulk electrolytic capacitor should be used between vcc and vss for each eight devices. the location of the capacitor should be close to where the power supply is connected to the array.
EN27C020 4800 great america parkway ste 202 tel: 408-235-8680 santa clara, ca. 95054 fax: 408-235-8685 preliminary 6 mode select table mode ce oe pgm a0 a1 a9 v pp output read v il v il x (2) xx x v cc d out output disable v il v ih xxxx v cc high z standby (ttl) v ih xx xxx v cc high z standby (cmos) v cc 0.3v xx xxx v cc high z program (4) v il v ih v il xx x v pp d in program verify v il v il v ih xx x v pp d out program inhibit v ih xx xxx v pp high z manufacturer code (3) v il v il x v il v ih vh (1) v cc 1c device code (3) v il v il x v ih v ih vh (1) v cc 02 notes: 1) vh = 12.0v 0.5v 2) x = either v ih or v il 3) for manufacturer code and device code, a1 = v ih when a1 = v il , both codes will read 7f 4) see dc programming characteristics for v pp voltage during programming eon's standard product identification code pins hex data code a0 a1 dq7 dq6 dq5 dq4 dq3 dq2 dq1 dq0 manufacturer 010001110 01c device type 110000001 0 02 continuation 000111111 17f 100111111 17f
EN27C020 4800 great america parkway ste 202 tel: 408-235-8680 santa clara, ca. 95054 fax: 408-235-8685 preliminary 7 figure 5. quikrite tm programming flow chart start x = 0 increment x x = 25? yes yes pass pass no fail fail no fail vcc = vpp = 5.25v device passed device failed vcc = 6.25v vpp = 12.75v interactive section verify section address = first location program one 10 s pulse increment address verify byte? verify all bytes? last address 20 note 1: either 100 m s or 20 m s pulse.
EN27C020 4800 great america parkway ste 202 tel: 408-235-8680 santa clara, ca. 95054 fax: 408-235-8685 preliminary 8 absolute maximum ratings storage temperature -65 y c to +125 y c ambient temperature with power applied -40 y c to +85 y c voltage with respect to v ss all pins except a9, v pp , v cc -0.6v to v cc + 0.5v a9, v pp -0.6v to +13.5v v cc -0.6v to +7.0v operating ranges commercial (c) case temperature(tc) 0 y c to +70 y c industrial (i) case temperature(tc) -40 y c to +85 y c supply read voltages +4.50v to +5.5v (functionality is guaranteed between these limits) stresses above those shown above may cause permanent damage to the device. this is a stress rating only and operation above these specifications for extended periods may affect device reliab ility. operation outside the "operating ranges" shown above voids any and all warranty provisions. dc characteristics for read operation symbol parameter min. max. unit conditions v oh output high voltage 2.4 v i oh = -0.4ma v ol output low voltage 0.45 v i ol = 2.1ma v ih input high voltage 2.0 v cc +0.5 v v il input low voltage -0.3 0.8 v i li input leakage current -5 5 m a v in = 0 to 5.5v i lo output leakage current -10 10 m a v out = 0 to 5.5v i cc3 v cc power -down current 10 m a ce = v cc 0.3v i cc2 v cc standby current 1.0 ma ce = v ih i cc1 v cc active current 30 ma ce = v il , f=5mhz, l out = 0ma i pp v pp supply current read 100 m a ce = oe = v il , v pp = 5.5v capacitance symbol parameter typ. max. unit conditions c in input capacitance 8 12 pf v in = 0v c out output capacitance 8 12 pf v out = 0v c vpp v pp capacitance 18 25 pf v pp = 0v
EN27C020 4800 great america parkway ste 202 tel: 408-235-8680 santa clara, ca. 95054 fax: 408-235-8685 preliminary 9 ac characteristics for read operation EN27C020 -45 -55 -70 -90 symbol parameter condition min max min max min max min max unit tacc (3) address to output delay ce = oe = v il 45 55 70 90 ns tce (2) ce to output delay oe = v il 45 55 70 90 ns toe (2, 3) oe to output delay oe = v il 25 25 30 35 ns tdf (4, 5) oe or ce high to output float, whichever occurred first 20 20 25 25 ns toh output hold from address, ce or oe, whichever occurred first 0000 ns note: please contact marketing department for other speed requirements. figure 6. ac waveforms for read operation ce address address valid oe output output valid tce tacc high z toe tdf toh
EN27C020 4800 great america parkway ste 202 tel: 408-235-8680 santa clara, ca. 95054 fax: 408-235-8685 preliminary 10 figure 7. output test waveforms and measurements ac driving levels ac measurement level 3.0v 1.5v 0.0v t r , t f < 5 ns (10% to 90%) ac driving levels ac measurement level output pin note: cl = 100pf including jig capacitance, except for the -45 and -55 devices, where cl = 30pf. 1.3v (1n914) 3.3k cl 2.4v 0.8 2.0 0.45v t r , t f < 20 ns (10% to 90%) 45 and 55 devices: output test load 70 and 90 devices: dc programming characteristics test limits symbol parameter conditions min. max units i li input load current v in = v il, v ih 5.0 m a v il input low level -0.5 0.8 v v ih input high level 0.7 v cc v cc + 0.5 v v ol output low voltage i ol = 2.1 ma 0.45 v v oh output high voltage i oh = -400 m a 2.4 v i cc2 v cc supply current 40 ma i pp2 v pp supply current ce = pgm = v il, 10 ma v id a9 product identification voltage 11.5 12.5 v
EN27C020 4800 great america parkway ste 202 tel: 408-235-8680 santa clara, ca. 95054 fax: 408-235-8685 preliminary 11 figure 8. programming waveforms address vih vil address stable data in program read (verify) data vih vil data out valid v cc 6.5v 5.0v v pp 13.0v 5.0v ce vih vil pgm vih vil oe vih vil tas toe tprt tds tdh tvcs tvps tpw toes tces tah tdfp
EN27C020 4800 great america parkway ste 202 tel: 408-235-8680 santa clara, ca. 95054 fax: 408-235-8685 preliminary 12 switching programming characteristics (t a = + 25 c 5 c) parameter symbol standard parameter description min. max units t as address setup time 2 m s t oes oe setup time 2 m s t ds data setup time 2 m s t ah address hold time 0 m s t dh data hold time 2 m s t dfp output enable to output float delay 0 130 ns t vps v pp setup time 2 m s t pw pgm program pulse width 20 105 m s t vcs v cc setup time 2 m s t ces ce setup time 2 m s t oe data valid from oe 150 ns ordering information EN27C020 45 p i temperature range (blank) = commercial ( 0 y c to +70 y c) i = industrial ( -40 y c to +85 y c) package p = 32 plastic dip j = 32 plastic plcc t = 32 plastic tsop speed 45 = 45ns 55 = 55ns 70 = 70ns 90 = 90ns base part number en = eon silicon devices 27 = eprom c = cmos 020 = 256k x 8

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